
1st
Workshop on EPIC (Explicitly Parallel Instruction Computing)
Architectures and Compiler Technology
Final Program
December
2nd, 2001
|
Sunday, December 2nd |
|
|
9:00AM |
Welcome-Dan Connors
(University of Colorado)-General Chair Carole Dulong (Intel Corporation) and Rick Hank (Hewlett Packard), Program Co-Chairs (Marriott Ballroom) |
|
9:00-9:30AM |
Keynote Speech: Dr. Wei Li, Principal Engineer and
manager of compiler development for the Itanium Processor Family in the Intel
Compiler Lab "Compiling for
the Itanium Architecture: Triumphs, Lessons, and Challenges" |
|
9:30- 10:00AM |
Session A: |
|
9:30-10:00AM |
Software pipelining
of loops with early exits for the Itanium architecture. Kalyan Muthujumar (Intel
Technology-India), Dong-Yuan Chen, Youfeng Wu (Intel Microprocessor
Research Labs) and Daniel M. Lavery (Intel Compiler Lab) |
|
10:00-10:30AM |
Predicate-Based
Transformations to Eliminate Control and Data-Irrelevant Cache Misses Ian Bratt, Alex Settle, and Dan
Connors (University of
Colorado-Boulder) |
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10:30-11:00AM |
Break |
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11:00- 12:30PM |
Session B: |
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11:00- 11:30AM |
EPIC Instruction Scheduling Based on Optimal Approaches. Steve Haga and Rajeev Barua (ECE-University of Maryland, College Park) |
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11:30- 12:00AM |
A Spill Code Reduction Technique for EPIC Architectures. Virgil Palanciuc, Dragos Badea, and Costel Ilas (Motorola DSP Center Romania) and Eric Flamand (Motorola Metrowerks France) |
|
12:00-12:30PM |
Incorporating Predicate Information Into Branch Predictors. Beth Simon, Brad Calder, and Jeanne Ferrante (University of California- San Diego) |
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12:30-2:00PM |
Lunch (provided) |
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2:00- 3:30PM |
Session C: |
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2:00- 2:30PM |
Fracture Mechanics on the Intel (R) Itanium
Architecture (A Case Study). Gerd Herber and Andrew Dolgert (Cornell Theory Center), Maxim Alt, Karen A. Mazurkiewicz, and Lynd Stringer (Intel Corporation). |
|
2:30- 3:00PM |
Dynamic Binary Instrumentation on IA-64. Vinodha Ramasamy and Robert Hundt (Dynamic Instrumentation Group, Hewlett Packard Company) |
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3:00- 3:30PM |
TRITANIUM: Augmenting the Trimaran Compiler Infrastructure To Support IA-64 Code Generation. Yogesh Chobe, Bhagi Narahari, Rahul Simha (George Washington University) and Weng-Fai Wong (National University of Singapore) |