Second Workshop on Explicitly Parallel Instruction Computing Architectures and Compiler Technology










CALL FOR PAPERS

EPIC-2
CALL FOR PAPERS
2nd Workshop on Explicitly Parallel Instruction
Computing Architectures and Compiler Technology
Held in conjunction with MICRO-35
Istanbul, Turkey

IMPORTANT FINAL SUBMISSION DEADLINE: September 30th!!!



The Explicitly Parallel Instruction Computing (EPIC) architecture model has the potential of achieving unparalleled levels of performance in future computer systems. The EPIC style of architecture was developed to enable higher levels of instruction-level parallelism. By allowing the compiler to express program parallelism and other relevant information directly to the processor, EPIC architectures can overcome hardware complexity issues that limit performance in traditional microprocessors. The major challenge to realizing the full potential of EPIC architectures is developing strategic compiler technologies that effectively deploy explicitly defined hardware mechanisms and deliver performance for both commercial and scientific applications. This one-day workshop will focus on promising research concepts that enable the EPIC architecture model.

TOPICS OF INTEREST

Topics of EPIC architectures and compiler technologies or related studies focusing on the following:
  • Predicated execution
  • Compiler-directed control speculation
  • EPIC performance monitoring unit feedback for dynamic compilation
  • Tools, compilers, and infrastructure for EPIC architectures
  • Compiler scheduling and optimization techniques for instruction-level parallelism
  • Data and value speculation
  • Hardware features to support instruction-level parallelism
  • Compiler controlled memory prefetching and memory hierarchy management
  • Support for software pipelining
  • Effects of architectural features on workload behavior
  • Novel architectures and micro-architectures
  • Experimental evaluation of Itanium microprocessors
  • Commercial and scientific workload studies for EPIC models
  • Power and energy aware computing techniques for EPIC machines
  • Performance analysis of EPIC architectures


    IMPORTANT DATES
    Submission Deadline: September 30, 2002 (no further extensions)
    Acceptances Mailed: October 22, 2002
    Final Version Due: November 11, 2002
    Workshop Date: November 18, 2002 (full day workshop)


    Full papers of up to 20 pages or extended abstracts of approximately 8 pages can be submitted. Clearly describe the nature of the work, its significance and the current status of the research. Include a title page containing the title of the paper, list of authors and their affiliations, addresses, telephone and fax numbers, email addresses and the name of the corresponding author.
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