2nd Workshop on Explicitly Parallel Instruction Computing Architecture and Compilers

Monday, November 18, 2002.
Istanbul, Turkey.

Workshop Program Proceedings are also available: Download

8:50am – 9am: Welcoming Remarks- David August (Princeton University)

9:00am – 10:30am : Session 1 Processor and Cache Performance

Invited Talk: Itanium Performance Insights[Abstract] [Paper]
John Sias, (University of Illinois-Urbana,Champaign).

Exploring and Optimizing Itanium2 Caches Performance for Scientific Code[Abstract] [Paper]
William Jalby and Christophe Lemuet (Prism, University of Versailles).

Compile-Time Cache Hint Generation for EPIC Architectures[Abstract][Paper]
Kristof Beyls and Erik H. D'Hollander (Ghent University).

10:30am – 11:00am: Coffee Break

11:00am – 12:30am: Session 2 Register Stack and Processor Performance

Performance Advantage of the Register Stack in Intel Itanium Processors[Abstract][Paper]
Ryan Rakvic, Ed Grochowski, Bryan Black, Murali Annavaram, Trung Diep, John P. Shen (Intel Corporation).

Reducing the Physical Cost of Large Register Files in EPIC Architectures
with Stacked Register Aliasing [Abstract][Paper]
Rohit Bhatia, Ron Arnold, and Don Soltis (HP Corporation).

Design and Experience: Using the Intel Itanium-2 Processor [Abstract][Paper]
Youngsoo Choi, Allan Knies, Geetha Vedaraman, Jeremiah Williamson,
and Irma Esmer (Presenter) (Intel Corporation).

12:30am – 2pm: Lunch

2:00pm – 3:30pm: Session 3  Optimization and Analysis Techniques

Optimal Global Scheduling for Itanium Processor Family[Abstract][Paper]
Sebastian Winkel (Saarland University Saarbrucken, Germany)

Procedure Boundary Elimination for EPIC Compilers [Abstract][Paper]
Spyridon Triantafyllis, Manish Vachharajani, and David I. August (Princeton University).

Predicate Analysis and If-Conversion in an Itanium Link-Time Optimizer [Abstract][Paper]
Noah Snavely, Saumya K. Debray, Gregory R. Andrews (University of Arizona).

3:30pm - EPIC-2 Ending Remarks (David August)