Dynamic Clock Scaling

Overview

Our design goals are simple.  Save energy without sacrificing performance.  There are many places in modern computers where the designer can look to save energy.  Because most computers do not consume all of their resources all of the time, slack can be exploited to either slow down computation or save energy by shutting off components while not in use.  We are looking at whether or not slack can be exploited to save energy on frequency/voltage scaling CPUs by dynamically scaling the voltage/frequency.

Energy is proportional to clock frequency and proportional to the SQUARE of the operating voltage.  Modern CPUs have a sliding scale of operating voltage vs. frequency.  In other words, raise the frequency, raise the voltage and vice versa.  Therefore, if we can lower the clock frequency (and lower the operating voltage to match), we can save energy even in the face of constant cycle requirement operations.

For example, an MPEG frame might take 50,000 cycles to decode.  The frame must be displayed by a certain deadline (the framerate).  If I decode the frame just in time to display it on the screen, running at a lower speed I save energy versus decoding the frame at full CPU and then sleeping for the remainder of the interval until display.

Another example would be a User Interface.  If human perception cannot tell the difference between 5 ms response time, and 50 ms response time, I should run the UI task more slowly and complete in 50 ms using a slower CPU frequency/voltage combination thereby saving energy.

So, we know we want to scale the CPU dynamically, and we want the control over CPU frequency/voltage to be set automatically.  There are still several hurdles to energy/performance nirvana.  The first question is, is there sufficient slack in the performance of tasks to scale the CPU?  The second question is, can the CPU be scaled quickly enough to save that energy without too much switching overhead?  Finally, and only if the answers two the first questions are positive, what or who controls the frequency/voltage scaling? We are exploring the answers to these questions.

Our Previous Work

We spent last year reviewing the current state of the art in operating systems level power savings.  We looked at work from Govil, Weiser, and Pering to determine if there was slack to exploit, and if we could use implied information about past process performance to determine future CPU frequency.  Initially, we were very hopeful that using only statistics about processes, we could scale for energy savings without losing performance.  Using a specially modified Itsy Pocket Computer from Compaq Western Research Labs we implemented these statistical mechanisms in a 2.0.30 Linux kernel and then evaluated there effectiveness.  We did not find good energy savings, not because there was not slack in the system, nor because we couldn't scale the voltage/frequency rapidly enough, but simply because past performance is not enough to allow aggressive scaling while still maintaining performance.  We presented this work at OSDI 2000.  It is available for download from this site as well.

Current Work

As a result, we have been looking into additional mechanisms for providing the scaling algorithm in the kernel with information upon which to make scaling decisions.

In a recent paper, Jacob Lorch explored using information about user interface deadlines to scale the processor to save energy.  We believe this approach has merit for this category of application, especially if the mechanism for communicating information to the scaling algorithm can be implemented in the user interface library code.

Another plan that we are exploring is using user land information to aid scaling.  If an application is rate based, (i.e. an mp3 decoder or dvd playback), there is significant internal knowledge about how long a frame of data takes to decode versus how much time exists between frames.  If this information can be transferred to the scaling algorithm, the process can be run to meet it's deadlines in a "just in time" fashion instead of decoding ahead of time and then sitting idle.  Recall that at one slower speed continuously saves more energy than running at full speed then idling because energy consumption varies with the square of the processor voltage, and scaling the frequency allows running at lower voltage.

Previously Published Research

Trevor Pering, Tom Burd, and Robert Brodersen.
The simulation of dynamic voltage scaling algorithms.
In IEEE Symposium on Low Power Electronics. IEEE Symposium on Low Power Electronics, 1995.
Kinshuk Govil, Edwin Chan, , and Hal Wasserman.
Comparing algorithms for dynamic speed-setting of a low-power cpu.
In Proceedings of The First ACM International Conference on Mobile Computing and Networking, Berkeley, CA, November 1995.
M. Weiser, B. Welch, A. Demers, and S. Shenker.
Scheduling for reduced cpu energy.
In First Symposium on Operating Systems Design and Implementation, pages 13-23, November 1994.
Trevor Pering.
Private communication.
J. Montanaro and et. al.
A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor.
In Digital Technical Journal, volume 9. Digital Equipment Corporation, 1997.
Dan Dobberpuhl.
The Design of a High Performance Low Power Microprocessor.
In International Symposium on Low Power Electronics and Design, pages 11-16, August 1996.
Trevor Pering, Tom Burd, and Robert Brodersen.
Voltage scheduling in the lparm microprocessor system.
In Proceedings of the 2000 International Symposium on Low Power Design, August 2000.
Thomas L. Martin.
Balancing Batteries, Power, and Performance: System Issues in CPU Speed-Setting for Mobile Computers.
PhD thesis, Carnegie Mellon University, 1999.
Keith I. Farkas, Jason Flinn, Godmar Back, Dirk Grunwald, and Jennifer Anderson.
Quantifying the energy consumption of a pocket computer and a java virtual machine.
In Proceedings of the ACM SIGMETRICS '00 International Conference on Measurement and Modeling of Computer Systems, 2000.
(to appear).
Transvirtual Technologies Inc.
Kaffe Java Virtual Machine.
http://www.transvirtual.com.

Jacob Lorch Sigmetrics Paper